Semiconductor memory device

ABSTRACT

A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.15/706,655, filed on Sep. 15, 2017, which claims priority under 35 U.S.C§ 119 of Korean Patent Application No. 10-2016-0173827, filed on Dec.19, 2016 in the Korean Intellectual Property Office, the disclosure ofwhich is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor memory device.

DISCUSSION OF RELATED ART

Semiconductor devices are highly integrated. Line widths of thesemiconductor devices are reduced using new exposure techniques and/orexpensive exposure techniques for high integration of the semiconductordevices.

SUMMARY

According to an exemplary embodiment of the present inventive concept, asemiconductor memory device is provided as follows. A substrate includesan active region. A bit line structure extends across the active region.A landing pad is disposed on an end portion of the active region. Afirst spacer is disposed between the bit line structure and the landingpad. A second spacer is disposed between the first spacer and thelanding pad. An air spacer is disposed between the first spacer and thesecond spacer. A capping pattern is disposed between a sidewall of thelanding pad and a sidewall of the bit line structure. The cappingpattern defines a top surface of the air spacer and comprises a metallicmaterial.

According to an exemplary embodiment of the present inventive concept, asemiconductor memory device is provided as follows. A substrate includesan active region. A bit line structure extends across the active region.A landing pad is disposed on an end portion of the active region. Afirst spacer is disposed between the bit line structure and the landingpad. A second spacer is disposed between the first spacer and thelanding pad. An air spacer is disposed between the first spacer and thesecond spacer. A capping pattern is disposed between a sidewall of thelanding pad and a sidewall of the bit line structure. The cappingpattern defines a top surface of the air spacer and comprisessubstantially the same material as the landing pad.

According to an exemplary embodiment of the present inventive concept, asemiconductor memory device is provided as follows. A substrate has afirst active region and a second active region. A stacked structure of astorage node contact, a landing pad and a data storage member stackedvertically on each other is disposed on the first active region of thesubstrate. A bit line adjacent to the stacked structure is disposed onthe second active region. A capping pattern protrudes away from asidewall of the landing pad in the stacked structure. An air gap isdisposed between a sidewall of the stacked structure and a sidewall ofthe bit line. An upper surface of the air gap is in contact with thecapping pattern.

BRIEF DESCRIPTION OF DRAWINGS

These and other features of the present inventive concept will becomemore apparent by describing in detail exemplary embodiments thereof withreference to the accompanying drawings of which:

FIG. 1 is a layout view illustrating a semiconductor memory deviceaccording to an exemplary embodiment of the present inventive concept;

FIG. 2A shows cross-sectional views taken along lines I-I′ and II-II′ ofFIG. 1 illustrating a semiconductor memory device according to anexemplary embodiment of the present inventive concept;

FIG. 2B shows an expanded view of a circled portion of FIG. 2A accordingto an exemplary embodiment of the present inventive concept;

FIG. 3A shows cross-sectional views taken along lines I-I′ and II-II′ ofFIG. 1 illustrating a semiconductor memory device according to anexemplary embodiment of the present inventive concept;

FIG. 3B shows an expanded view of a circled portion of FIG. 3A accordingto an exemplary embodiment of the present inventive concept;

FIGS. 4A to 11A are layout views illustrating a method of fabricating asemiconductor memory device according to an exemplary embodiment of thepresent inventive concept; and

FIGS. 4B to 11B and 11C are cross-sectional views taken along lines I-I′and II-II′ of FIGS. 4A to 11A illustrating a method of fabricating asemiconductor memory device according to an exemplary embodiment of thepresent inventive concept.

Although corresponding layout views and/or perspective views of somecross-sectional view(s) may not be shown, the cross-sectional view(s) ofdevice structures illustrated herein provide support for a plurality ofdevice structures that extend along two different directions as would beillustrated in a layout view, and/or in three different directions aswould be illustrated in a perspective view. The two different directionsmay or may not be orthogonal to each other. The three differentdirections may include a third direction that may be orthogonal to thetwo different directions. The plurality of device structures may beintegrated in a same electronic device. For example, when a devicestructure (e.g., a memory cell structure or a transistor structure) isillustrated in a cross-sectional view, an electronic device may includea plurality of the device structures (e.g., memory cell structures ortransistor structures), as would be illustrated by a layout view of theelectronic device. The plurality of device structures may be arranged inan array and/or in a two-dimensional pattern.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present inventive concept will be describedbelow in detail with reference to the accompanying drawings. However,the inventive concept may be embodied in different forms and should notbe construed as limited to the embodiments set forth herein. In thedrawings, the thickness of layers and regions may be exaggerated forclarity. It will also be understood that when an element is referred toas being “on” another element or substrate, it may be directly on theother element or substrate, or intervening layers may also be present.It will also be understood that when an element is referred to as being“coupled to” or “connected to” another element, it may be directlycoupled to or connected to the other element, or intervening elementsmay also be present. Like reference numerals may refer to the likeelements throughout the specification and drawings.

As used herein, singular “a,” “an,” and “the” are intended to cover theplural forms as well, unless the context clearly indicates otherwise.

FIG. 1 is a layout view illustrating a semiconductor memory deviceaccording to an exemplary embodiment of the present inventive concept.FIG. 2A is a cross-sectional view taken along lines I-I′ and II-II′ ofFIG. 1 illustrating a semiconductor memory device according to exemplaryembodiment of the present inventive concept.

Referring to FIGS. 1 and 2A, a device isolation layer 102 may bedisposed in a substrate 100. The substrate 100 may be a bulk siliconsubstrate, a silicon on insulator (SOI) substrate, a germaniumsubstrate, a germanium on insulator (GOI) substrate, a silicon-germaniumsubstrate, a III-V group compound semiconductor substrate, or anepitaxial thin-film substrate obtained by performing a selectiveepitaxial growth (SEG) process.

The device isolation layer 102 may include an insulating material (e.g.,silicon oxide). The device isolation layer 102 may define a plurality ofactive regions AR of the substrate 100. The plurality of active regionsAR each may have a bar shape elongated in a third direction Z. Theactive regions AR may be parallel to each other in the third directionZ. The layout view of FIG. 1 may be described using a first direction Xand a second direction Y. The third direction Z may be a directionbetween the first direction X and the second direction Y. The first,second and third directions X, Y and Z are extended on the same plane.

Source/drain regions 50 may be disposed in the active regions AR. Forexample, each of the source/drain regions 50 may be disposed in one ofthe active regions AR. The source/drain regions 50 may have conductivitydifferent from conductivity of the substrate 100. For example, thesource/drain regions 50 may have N-type conductivity and the substrate100 may have P-type conductivity.

Word lines WL may be disposed in the substrate 100. Two word lines WLmay run across one active region AR in the first direction X crossingthe third direction Z. The word lines WL may have top surfaces lowerthan a top surface 100 a of the substrate 100. For example, the wordlines WL may be buried in the substrate 100. The word lines WL may beformed of a conductive material, for example, impurity-dopedpolysilicon, metal, or metal silicide.

Gate dielectric layers 108 may be disposed in the substrate 100. Forexample, each of the gate dielectric layers 108 may be between thesubstrate 100 and sidewalls of one of the word lines WL and between thesubstrate 100 and a bottom surface of one of the word lines WL. The gatedielectric layers 108 may include, for example, a silicon oxide layer, athermal oxide layer, or a high-k dielectric layer.

Gate protection patterns 110 may be disposed on top surfaces of the wordlines WL and top surfaces of the gate dielectric layers 108. Forexample, each of the gate protection patterns 110 may be disposed on topsurfaces of one of the word lines WL and one of the gate dielectriclayers 108. The gate protection patterns 110 each may have a top surfaceat substantially the same level as the top surface 100 a of thesubstrate 100. The gate protection patterns 110 may include aninsulating material (e.g., silicon oxide).

A buffer layer 112 may be disposed on the top surface 100 a of thesubstrate 100. The buffer layer 112 may cover the top surfaces of thegate protection patterns 110. The buffer layer 112 may include one ormore insulation layers. For example, the buffer layer 112 may include asilicon oxide layer, a silicon nitride layer, a silicon oxynitridelayer, or a combination thereof.

Bit line node contacts DCC may be disposed on the active regions AR. Forexample, each of the bit line node contacts DCC may be disposed on acentral portion of one of the active regions AR between two adjacentword lines WL of the word lines WL running across the one of the activeregions AR. For example, two adjacent word lines WL of the word lines WLmay extend in the first direction (X-axis) over the one of the activeregions AR. In this case, one of the bit line node contacts DCC may bedisposed at the central portion of the one of the active regions AR, theone of the bit line node contacts DCC being disposed between one of thetwo adjacent word lines WL and the other of the two adjacent word linesWL and the one of the bit line node contacts DCC partially overlappingthe two adjacent word lines WL. Each of the bit line node contacts DCCmay penetrate the buffer layer 112 to be electrically connected to oneof the active regions AR. For example, each of the bit line nodecontacts DCC may be electrically connected to one of the source/drainregions 50 between one of two adjacent word lines WL and the other ofthe two adjacent word lines WL. Each of the bit line node contacts DCCmay have a bottom surface at a level between the top surface 100 a ofthe substrate 100 and the top surfaces of the word lines WL. The bitline node contacts DCC may include, for example, impurity-dopedpolysilicon.

Buried patterns 125 each may be buried in a central portion of one ofthe active regions AR and may cover a sidewall of one of the bit linenode contacts DCC. The buried patterns 125 may include, for example,silicon nitride. In an exemplary embodiment, the bit line node contactsDCC each may be disposed between two adjacent buried patterns 125, eachof which is disposed under one of air spacers ASP.

Bit line structures BLS may be disposed extending in a second directionY crossing the first and third directions X and Z. The first directionX, the second direction Y and the third direction Z may be in a sameplane. The bit line structures BLS may overlap the bit line contacts DCCarranged in the second direction Y. For example, each of the bit linestructures BLS may be electrically connected to a predetermined numberof the bit line node contacts DCC arranged in the second direction Y.

Each of the bit line structures BLS may include a bit line BL and aninsulation pattern 120 that are sequentially stacked on one of the bitline node contacts DCC. The bit line BL may include a first conductivepattern 116 and a second conductive pattern 118 stacked on each other.The first conductive pattern 116 may include, for example,impurity-doped polysilicon. The second conductive pattern 118 mayinclude, for example, tungsten (W), aluminum (Al), copper (Cu), nickel(Ni), or cobalt (Co). The insulation pattern 120 may be disposed on thesecond conductive patterns 118. In this case, the second conductivepattern 118 may be interposed between the first conductive pattern 116and the insulation pattern 120. The insulation pattern 120 may include,for example, a silicon oxide layer. As not shown in figures, a diffusionbarrier layer may be disposed between the first conductive pattern 116and the second conductive pattern 118.

Storage node contacts BC may be disposed on the active regions AR. In anexemplary embodiment, a pair of storage node contacts BC may overlap oneof the active regions AR. For example, one of the pair of storage nodecontacts BC may overlap a first end portion AR-1E of the one of theactive regions AR, and the other of the pair of storage node contacts BCmay overlap a second end portion AR-2E of the one of the active regionsAR. In this case, the first end portion AR-1E and the second end portionAR-2E may be arranged along in parallel to the third direction Z. Thepair of storage node contacts BC may be electrically connected to a pairof the source/drain regions 50 disposed in each of the active regionsAR. One of the pair of the source/drain regions 50 may be disposed inthe first end portion AR-1E of the one of the active regions AR. Theother of the pair of the source/drain regions 50 may be disposed in thesecond end portion AR-2E of the one of the active regions AR.

Each of the pair of storage node contacts BC may have a lower portionthat penetrates through the buffer layer 112, extending into one of thepair of the source/drain regions 50 disposed in each of the activeregions AR. Each of the storage node contacts BC may have a top surfacehigher than a top surface of the buffer layer 112. The storage nodecontacts BC may include, for example, impurity-doped polysilicon.

Separation patterns 130 each may be disposed at an intersection whereeach of the word lines WL intersects a space between two adjacent bitline structures BLS. For example, each of the separation patterns 130may be disposed on the buffer layer 112 and between two storage nodecontacts BC adjacent to each other in the second direction Y. Theseparation patterns 130 may include, for example, SiBCN, SiCN, SiOCN, orSiN.

Landing pads LP each may be disposed on one of the storage node contactsBC. For example, each of the landing pads LP may be electricallyconnected to one of the storage node contacts BC. The landing pads LPmay be physically and electrically spaced apart from each other. Each ofthe landing pads LP may shift in the first direction X relative to acenter of one of the storage node contacts BC. For example, each of thelanding pads LP may overlap one of the storage node contacts BC and acenter of each of the landing pads LP need not coincide with the centerof the one of the storage node contacts BC. Accordingly, the landingpads LP each may have a portion overlapping its adjacent one of the bitline structure BLS and another portion overlapping its adjacent one ofthe storage node contacts BC. The landing pads LP each may include abarrier pattern 134 and a metal pattern 136 that are sequentiallystacked on one of the storage node contacts BC. The barrier pattern 134may include, for example, TiN, Ti/TiN, TiSiN, TaN, or WN. The metalpattern 136 may include, for example, tungsten (W).

Residual patterns 137 each may surround a sidewall of one of the landingpads LP. For example, the landing pads LP each may have a sidewall and alower portion adjacent to one of the storage node contacts BC. The lowerportion of each of the landing pads LP may be partially exposed throughone of the residual patterns 137. For example, the residual patterns 137each may expose a portion of the barrier pattern 134 and a portion ofthe metal pattern 136 at the lower portion of each of the landing padsLP. The residual patterns 137 may include an insulating material (e.g.,silicon nitride).

A first spacer SP1 and a second spacer SP2 may be sequentially disposedon a sidewall of each of the bit line structures BLS. The first andsecond spacers SP1 and SP2 may extend in the second direction Y alongthe sidewall of each of the bit line structures BLS. For example, thefirst spacer SP1 may extend in the second direction Y between one of thelanding pads LP and the bit line BL adjacent to the one of the landingpads LP and between one of the storage node contacts BC and the bit lineBL adjacent to the one of the storage node contacts BC. The secondspacer SP2 may extend between the one of the landing pads LP and thefirst spacer SP1 and between the first spacer SP1 and one of the storagenode contacts BC. Portions of the first and second spacers SP1 and SP2may be disposed in a space between the landing pads LP adjacent to eachother in the first direction X. A combined structure of the barrierpattern 134 and the metal pattern 136 may have a first portionconstituting a lower sidewall of each of the landing pads LP, and asecond portion exposed through the residual pattern 137 and the secondspacer SP2 to a space between the landing pads LP adjacent to each otherin the first direction X. The first and second spacers SP1 and SP2 mayinclude, for example, silicon nitride.

Capping patterns CP each may be disposed between a sidewall of one ofthe insulation pattern 120 and the lower sidewall of one of the landingpads LP. In an exemplary embodiment, the capping patterns CP each may bein contact with the sidewall of one of the insulation patterns 120 andthe lower sidewall of one of the landing pads LP. In an exemplaryembodiment, the capping patterns CP each may be in contact with thesidewall of one of the insulation patterns 120, the lower sidewall ofone of the landing pads LP, and top surfaces of the first and secondspacers SP1 and SP2. In this configuration, the capping patterns CP eachmay be in contact with a portion of the barrier pattern 134, a portionof the metal pattern 136, or a portion of both, that constitute thelower sidewall of one of the landing pads LP. For example, the cappingpatterns CP each may be in contact with at least one of the metalpattern 136 and the barrier pattern 134.

In an exemplary embodiment, the capping patterns CP each may be incontact with the lower sidewall of one of the landing pads LP, butspaced apart from the sidewall of one of the insulation patterns 120.(FIGS. 2B and 3B). In this case, a first gap-fill layer 138 a may coveran upper surface of an air spacer ASP. The first gap-fill layer 138 aand the air spacer ASP will be described later.

In an exemplary embodiment, the capping patterns CP each may be incontact with the lower sidewall of one of the landing pads LP and thetop surface of the second spacer SP2, but spaced apart from the topsurface of the first spacer SP1 and the sidewall of one of theinsulation patterns 120. (FIG. 2B).

In an exemplary embodiment, the capping patterns CP each may be incontact with the lower sidewall of one of the landing pads LP, butspaced apart from the sidewall of one of the insulation patterns 120 andthe top surfaces of the first and second spacers SP1 and SP2. (FIG. 3B).In this configuration, the capping patterns CP each may be in contactwith a portion of the barrier pattern 134 or a portion of the metalpattern 136. The portion of the barrier pattern 134 and the portion ofthe metal pattern 136 may constitute the lower sidewall of the landingpad LP.

In an exemplar embodiment, the capping patterns CP each may includemetal nitride selectively grown on the lower sidewall of one of thelanding pads LP. For example, the capping patterns CP may include amaterial, which is the same as a material of the barrier pattern 134,selectively grown on a portion of the barrier pattern 134 exposedthrough the residual pattern 137 and the second spacer SP2. In thiscase, the capping patterns CP each may extend away from the portion ofthe barrier pattern 134. For example, the capping patterns CP mayinclude TiN. The present inventive concept is not limited thereto. Forexample, the capping patterns CP may include Ti/TiN.

The capping patterns CP each may partially or completely cover or closean upper portion of a space between the first and second spacers SP1 andSP2. The capping patterns CP each may therefore define an air spacer ASPbetween the first and second spacers SP1 and SP2. For example, thecapping patterns CP each may define a top surface of the air spacer ASP,and the first and second spacers SP1 and SP2 may define sidewalls of theair spacer ASP. The air spacer ASP may be filled with air. The airspacer ASP may extend in the second direction Y between the first andsecond spacers SP1 and SP2. For example, the top surface of the airspacer ASP may be positioned higher than the top surface of the storagenode contact BC.

A first gap-fill layer 138 a and a second gap-fill layer 138 b maysequentially fill a space between two adjacent landing pads LP. Thefirst gap-fill layer 138 a may surround outer sidewalls of the landingpads LP. The second gap-fill layer 138 b may be disposed on the firstgap-fill layer 138 a and completely fill the space between the twoadjacent landing pads LP. For example, the first and second gap-filllayers 138 a and 138 b may include TEOS (tetraethlyorthosilicate), highdensity plasma (HDP) oxide, silicon oxide, silicon nitride, or siliconcarbonitride.

Data storage members DSM may be disposed on the landing pads LP. Thedata storage members DSM each may be, for example, a capacitor. Thecapacitor may include a bottom electrode BE, a dielectric layer DL, anda top electrode TE. For example, the bottom electrodes BE may bearranged in a zigzag manner along the second direction Y.

FIG. 3A is a cross-sectional view taken along lines I-I′ and II-II′ ofFIG. 1 illustrating a semiconductor memory device according to anexemplary embodiment of the present inventive concept. For brevity ofthe description, those components substantially the same as thosediscussed in the semiconductor memory device of FIG. 2 are allocated thesame reference numerals thereto, and a repetitive explanation thereofwill be omitted.

Referring to FIG. 3A, the capping patterns CP each may include ametallic material selectively grown on the lower sidewall of one of thelanding pads LP. For example, the capping patterns CP may include amaterial, which is the same as a material of the metal pattern 136,selectively grown on a portion of the metal pattern 136 exposed throughthe residual pattern 137 and the second spacer SP2. In this case, thecapping patterns CP each may extend away from the portion of the metalpattern 136. For example, the capping patterns CP may include tungsten(W). In this case, the capping patterns CP may be spaced apart from atop surface of the first spacer SP1 and a top surface of the secondspacer SP2. (See also, FIG. 3B).

Upper metal patterns MP each may be disposed between the bottomelectrode BE and the landing pad LP. The upper metal pattern MP mayinclude the same material as the landing pad LP and the capping patternCP. The upper metal pattern MP may include, for example, tungsten (W).The present inventive concept is not limited thereto. For example, theupper metal pattern MP may include tungsten (W) and Ti/TiN or tungsten(W) and TiN.

FIGS. 4A to 11A are layout views illustrating a method of fabricating asemiconductor memory device according to an exemplary embodiment of thepresent inventive concept. FIGS. 4B to 11B and 11C are cross-sectionalviews taken along lines I-I′ and II-IP of FIGS. 4A to 11A illustrating amethod of fabricating a semiconductor memory device according to anexemplary embodiment of the present inventive concept.

Referring to FIGS. 4A and 4B, active regions AR may be defined byforming a device isolation layer 102 in a substrate 100. The deviceisolation layer 102 may be formed by forming first trenches 131A in thesubstrate 100 and then filling the first trenches 131A with aninsulating material. The active regions AR each may have a bar shapeelongated in a third direction Z and be disposed in parallel to eachother. The substrate 100 may be a bulk silicon substrate, a silicon oninsulator (SOI) substrate, a germanium substrate, a germanium oninsulator (GOI) substrate, a silicon-germanium substrate, or anepitaxial layer substrate obtained by performing selective epitaxialgrowth (SEG). The device isolation layer 102 may include, for example,silicon oxide, silicon nitride, or silicon oxynitride.

Source/drain regions 50 may be formed in the active regions AR. Thesource/drain regions 50 may be formed in non-overlapped regions betweenthe active regions AR and word lines WL. For example, three source/drainregions 50 may be formed in each of the active regions AR. Thesource/drain regions 50 may be formed by forming an ion implantationmask (not shown) on the substrate 100 and then performing an ionimplantation process on the substrate 100 exposed through the ionimplantation mask. Alternatively, the ion implantation process may becarried out without the ion implantation mask. The source/drain regions50 may have conductivity (e.g., N-type) different from that of thesubstrate 100.

Second trenches 131B may be formed in the substrate 100 having thedevice isolation layer 102. A pair of the second trenches 131B may beformed running across each of the active region AR in a first directionX crossing the third direction Z. The second trenches 131B may beparallel to each other. A gate dielectric layer 108 may be formed toconformally cover a surface of each of the second trenches 131B. Thegate dielectric layer 108 may include an insulating material layer, forexample, a silicon oxide layer, a thermal oxide layer, or a high-kdielectric layer.

The word lines WL may be formed in the second trenches 131B includingthe gate dielectric layer 108 formed therein. The word lines WL may beformed by forming on the gate dielectric layer 108 a metal layer (notshown) to fill the second trenches 131B and then performing an etchprocess on the metal layer to leave portions of the metal layer on lowerportions of the second trenches 131B. For example, the metal layer maybe recessed so that top surfaces of the word lines WL are positionedbelow a top surface of the substrate 100 in the etch process. In thiscase, the second trenches 131B may be partially filled with the wordlines WL at lower portions of the second trenches 131B. In an exemplaryembodiment, the gate dielectric layer 108 may be etched at substantiallythe same time with the metal layer in the etch process. The word linesWL may include a conductive material, for example, doped polysilicon,metal, or metal silicide.

Gate protection patterns 110 may be formed to fill remaining portions ofthe second trenches 131B. The gate protection patterns 110 each may beformed on one of the word lines WL and may completely fill the secondtrenches 131B. For example, a combined structure of one of the wordlines WL and one of the gate protection patterns 110 stacked on eachother may fill completely one of the second trenches 131B. The gateprotection patterns 110 may include, for example, silicon oxide, siliconnitride, or silicon oxynitride.

Referring to FIGS. 5A and 5B, a buffer layer 112 may be formed on thesubstrate 100. For example, the buffer layer 112 may be formed on theresulting structure of FIGS. 4A and 4B. The buffer layer 112 may includeone or more insulation layers. The buffer layer 112 may include, forexample, a silicon oxide layer, a silicon nitride layer, a siliconoxynitride layer, or a combination thereof. As not shown in figures, amask pattern including openings may be formed on the buffer layer 112.For example, the openings of the mask pattern may define regions wherebit line node contacts DCC are to be formed.

An etch process may be performed to pattern the substrate 100 and thebuffer layer 112 exposed through the mask pattern. The etch process maypartially etch the buffer layer 112 and an upper portion of thesubstrate 100 to form first contact holes CH1 in the active regions AR.For example, the first contact holes CH1 each may be formed by etching acentral portion of each of the active regions AR that is exposed betweenone of a pair of word lines WL and the other of the pair of word linesWL. The pair of word lines WL may be disposed on one of the activeregions AR, running across the one of the active regions AR. The etchprocess may therefore expose the source/drain regions 50 formed in thecentral portions of the active regions AR. The etch process for formingthe first contact holes CH1 may also partially etch an upper portion ofthe device isolation layer 102 adjacent to the source/drain region 50.For example, the source/drain region 50 formed in the central portion ofthe active region AR may be shared by a pair of word lines WL disposedon the active region AR.

The bit line node contacts DCC each may be formed in one of the firstcontact holes CH1. The bit line node contacts DCC may completely fillthe first contact holes CH1. For example, the bit line node contacts DCCeach may be formed by forming on the buffer layer 112 a conductive layer(not shown) to fill the first contact holes CH1 and then performing aplanarization process (e.g., CMP or etch-back) on the conductive layeruntil exposing a top surface of the buffer layer 112. The bit line nodecontacts DCC may include impurity-doped polysilicon, metal silicide,polysilicide, metal nitride, or metal.

A first electrode layer 231 and a second electrode layer 233 may besequentially formed on the buffer layer 112. The first electrode layer231 may include, for example, impurity-doped polysilicon. The secondelectrode layer 233 may include, for example, tungsten (W), aluminum(Al), copper (Cu), nickel (Ni), or cobalt (Co). As not shown in figures,a diffusion barrier layer may be formed between the first and secondelectrode layers 231 and 233. The diffusion barrier layer may include adiffusion barrier metal, for example, TiN, Ti/TiN, TiSiN, TaN, or WN.

Insulation patterns 120 may be formed on the second electrode layer 233.The insulation patterns 120 may extend in a second direction Y crossingthe first and third directions X and Z, and may be in parallel to eachother. Each of the insulation patterns 120 may run across the activeregions AR to pass over the bit line node contacts DCC arranged in thesecond direction Y. The insulation patterns 120 may include, forexample, silicon oxide or silicon nitride.

Referring to FIGS. 6A and 6B, bit lines BL may be formed by using theinsulation patterns 120 as an etch mask to sequentially pattern thesecond electrode layer 233 and the first electrode layer 231. Each ofthe bit lines BL may include a first conductive pattern 116 and a secondconductive pattern 118 that are sequentially formed on the substrate 100when the first electrode layer 231 and the second electrode layer 233are patterned, respectively. The bit lines BL each may run across theactive regions AR in the second direction Y and pass over the bit linenode contacts DCC arranged in the second direction Y.

After the bit lines BL are formed, an etch process may be performed topartially etch the bit line node contacts DCC exposed through the bitlines BL, thereby reducing a width of each of the bit line node contactsDCC. Due to the reduction of the width of the bit line node contact DCC,a hollow space may be formed between each of the first contact holes CH1and each of the bit line node contacts DCC. For example, the hollowspace may be formed within each of the first contact holes CH1.

Buried patterns 125 may be formed in the hollow space of each of thefirst contact holes CH1. The buried patterns 125 may be formed byforming an insulation layer to completely fill the first contact holeCH1 and to cover sidewalls of the bit lines BL and sidewalls and topsurfaces of the insulation patterns 120, and then by performing an etchprocess on the insulation layer. Through these processes, the buriedpatterns 125 may be locally formed in the first contact hole CH1. Theburied patterns 125 may include, for example, silicon nitride.

A first spacer layer 301 may be formed to conformally cover thesidewalls of the bit lines BL, the sidewalls and top surfaces of theinsulation patterns 120, and the top surface of the buffer layer 112.The first spacer layer 301 may include, for example, silicon nitride. Asacrificial spacer layer 303 may be formed on the first spacer layer301. The sacrificial spacer layer 303 may conformally cover a surface ofthe first spacer layer 301. The sacrificial spacer layer 303 may includea material having etch selectivity with respect to the first spacerlayer 301. For example, the sacrificial spacer layer 303 may includesilicon oxide. A second spacer layer 305 may be formed on thesacrificial spacer layer 303. The second spacer layer 305 mayconformally cover a surface of the sacrificial spacer layer 303. Thesecond spacer layer 305 may include a material having etch selectivitywith respect to the sacrificial spacer layer 303. For example, thesecond spacer layer 305 may include silicon nitride.

Referring to FIGS. 7A and 7B, an etch-back process may be performed onthe resulting structure of FIGS. 6A and 6B. For example, in theetch-back process, the second spacer layer 305, the sacrificial spacerlayer 303, and the first spacer layer 301 may be sequentially etched andthe top surfaces of the insulation patterns 120 and the top surface ofthe buffer layer 112 may be exposed. Accordingly, first spacers SP1,sacrificial spacers 303 a, and second spacers SP2 may be formed on thesidewalls of the bit lines BL and the sidewalls of the insulationpatterns 120.

Sacrificial patterns SCP may be formed at first intersections IS-1 whereend portions of the active regions AR intersect spaces between the bitlines BL. For example, the first intersections IS-1 each may be a regionwhere one end portion of each of the active regions AR and a spacedefined between two adjacent bit lines BL overlap each other. The spacemay be extended in parallel to the two adjacent bit lines BL along thesecond direction (Y-axis). In addition, separation patterns 130 may beformed at second intersections IS-2 where the word lines WL intersectthe spaces between the bit lines BL. For example, the secondintersections IS-2 each may be a region where each of the word lines WLand the space defined between two adjacent bit lines BL overlap eachother. The sacrificial patterns SCP may be formed by forming aninsulation layer (not shown) to fill the spaces between the bit lines BLand then performing a planarization process on the insulation layer. Theseparation patterns 130 may be formed to fill spaces between thesacrificial patterns SCP adjacent to each other in the second directionY. The top surfaces of the insulation patterns 120 may be coplanar withtop surfaces of the sacrificial pattern SCP and top surfaces of theseparation pattern 130 at substantially the same height from the topsurface of the substrate 100. The separation patterns 130 may include amaterial having etch selectivity with respect to the sacrificialpatterns SCP. In an exemplary embodiment, the separation patterns 130and the sacrificial patterns SCP may be formed of different materials ordifferent material combinations. The sacrificial patterns SCP mayinclude, for example, silicon oxide, silicon nitride, or siliconoxynitride. The separation patterns 130 may include, for example, SiBCN,SiCN, SiOCN, or SiN.

Referring to FIGS. 8A and 8B, second contact holes CH2 may be formed byetching the sacrificial patterns SCP, portions of the buffer layer 112,and a partial upper portion of the substrate 100. The second contactholes CH2 may expose the source/drain regions 50 formed in end portionsof the active regions AR. For example, the end portions of the activeregions AR may be positioned in the first intersection IS-1 of FIG. 7A.The second contact holes CH2 may expose sidewalls of the second spacersSP2.

Storage node contacts BC may be formed in the second contact holes CH2.The storage node contacts BC may be formed by forming a conductive layer(not shown) to fill the second contact holes CH2 and also to cover thetop surfaces of the insulation patterns 120. Then the conductive layermay undergo a planarization process to expose the top surfaces of theinsulation patterns 120. Successively, upper portions of the remainingconductive layer localized within the second contact holes CH2 mayundergo a first etch process such that the remaining conductive layermay be recessed from the top surfaces of the insulation patterns 120 toform preliminary storage node contacts BC-P. In the first etch process,the second spacers SP2 each may have an inner sidewall SP2-I exposed inone of the second contact holes CH2. For example, the inner sidewallSP2-I of each of the second spacers SP2 may be partially in contact withone of the preliminary storage node contacts BC-P. A top surface of thepreliminary storage node contacts BC-P are represented with a dashedline in FIG. 8B. The preliminary storage node contacts BC-P may include,for example, impurity-doped polysilicon.

A second etch process may be performed to etch upper portions of thesecond spacers SP2 exposed through the preliminary storage node contactsBC-P and also etch upper portions of the sacrificial spacers 303 acovering the upper sidewalls of the second spacers SP2. Therefore, thefirst spacers SP1 each may have an inner sidewall SP-I exposed in one ofthe second contact holes CH2. For example, the inner sidewall SP1-I ofeach of the first spacers SP1 may be partially in contact with thesacrificial spacers 303 a. The preliminary storage node contacts BC-Pmay have the top surfaces at the same level as top surfaces of thesecond spacers SP2 and the sacrificial spacers 303 a.

Upper portions of the preliminary storage node contacts BC-P may undergoa third etch process such that the preliminary storage node contactsBC-P may be recessed from the top surfaces of the second spacers SP2 andthe top surfaces of the sacrificial spacers 303 a to form the storagenode contacts BC. Therefore, the inner sidewall SP2-I of each of thesecond spacers SP2 may be partially exposed by one of the storage nodecontacts BC.

Referring to FIGS. 9A and 9B, landing pads LP may be formed on thestorage node contacts BC. For example, the formation of the landing padsLP may include the followings: forming a barrier layer (not shown) toconformally cover top surfaces of the storage node contacts BC, topsurfaces and upper inner sidewalls of the second spacers SP2, topsurfaces of the sacrificial spacers 303 a, upper inner sidewalls and topsurfaces of the first spacers SP1, and top surfaces of the insulationpatterns 120; forming on the barrier layer a metal layer (not shown) tofill the second channel holes CH2; and sequentially patterning thebarrier layer and the metal layer to form the landing pads LP. Thepatterning process may form an internal space O between two landing padsLP. Each of the landing pads LP may include a barrier pattern 134 and ametal pattern 136 that are sequentially formed on each of the storagenode contacts BC. For example, the internal space O may separate twoadjacent landing pads LP along the first direction (X-axis).

A peripheral circuit layer 320 may be formed to conformally cover topsurfaces and sidewalls of the landing pads LP and also cover portions oftop surfaces of the insulation patterns 120 exposed through the landingpads LP. In a semiconductor memory device according to an exemplaryembodiment of the present inventive concept, the peripheral circuitlayer 320 may be formed on a peripheral circuit region provided withtransistors by which the semiconductor memory device is operated. Theperipheral circuit layer 320 may include, for example, silicon nitride.

Referring to FIGS. 10A and 10B, an etch process may be performed to etcha bottom surface of the internal space O and expose top surfaces of thesacrificial spacers 303 a. The etch process may be performed such thatthe peripheral circuit layer 320 is partially etched on its portioncovering the top surfaces of the landing pads LP and the bottom surfaceof the internal space O, which may form residual patterns 137 coveringsidewalls of the lading pads LP. The first and second spacers SP1 andSP2 may be exposed on their top surfaces when the top surfaces of thesacrificial spacers 303 a are exposed. In addition, in the internalspace O, the etch process may partially expose the sidewalls of thelanding pads LP through the second spacers SP2 and the residual patterns137. For example, in the internal space O, the sidewall of each of thelanding pads LP may have a lower portion, which is adjacent to each ofthe first spacers SP1. For example, the lower portion of the sidewall ofeach of the landing pads LP may be composed of a portion of the barrierpattern 134 and a portion of the metal pattern 136. The etch process mayinclude a dry etch process.

A selective removal may be performed on the sacrificial spacers 303 aexposed to the internal space O. The internal space O may thereforeextend between first and second spacers SP1 and SP2. Due to the removalof the sacrificial spacers 303 a, inner sidewalls SP1-I of the firstspacers SP1, outer sidewalls SP2-O of the second spacers SP2, andportions of the storage node contacts BC may be exposed to the internalspace O. The sacrificial spacers 303 a may be removed by using an etchrecipe having etch selectivity with respect to the first and secondspacers SP1 and SP2. The sacrificial spacers 303 a may be removed by awet etch process that uses an etchant such as, for example, hydrofluoricacid (HF) or a chemical solution containing HF and NH₄F (“LAL”).

Referring to FIGS. 11A and 11B, capping patterns CP may be formed onportions of the sidewalls of the landing pads LP exposed from the secondspacers SP2 and the residual patterns 137. The capping patterns CP maycover or close upper portions of spaces formed between the first andsecond spacers SP1 and SP2, and thus air spacers ASP may be definedbetween the first and second spacers SP1 and SP2. For example, thecapping patterns CP may define top surfaces of the air spacers ASP. Forexample, the air spacers ASP each may be defined by the inner sidewallSP1-I of each of the first sidewalls SP1, the outer sidewall SP2-O ofeach of the second sidewalls SP2, a bottom surface of each of thecapping patterns CP and a portion of each of the storage node contactsBC. In this case, the portion of each of the storage node contacts BCmay be exposed between a lower end of each of the second spacer SP2 anda bottom portion of each of the first spacers SP1. In an exemplaryembodiment, the bottom portion of each of the first spacers SP1 may bein contact with one of the buried patterns 125 or the buffer layer 112.

Each of the capping patterns CP may be selectively grown from thebarrier pattern 134, or the metal pattern 136, or both that are exposedfrom each of the second spacers SP2 and each of the residual patterns137. For example, the capping patterns CP may be formed by anarea-selective deposition process. The capping patterns CP may be grownfrom one or more of the barrier pattern 134 and the metal pattern 136until contacting a sidewall of the insulation pattern 120 to completelycover or enclose the upper portion of the spaces between the first andsecond spacers SP1 and SP2.

In an exemplary embodiment, the capping patterns CP may be grown fromthe barrier pattern 134, or the metal pattern 136, or both, to theextent that the capping patterns CP are not in contact with a sidewallof the insulation pattern 120. In this case, the capping patterns CP maycover or enclose incompletely the upper portion of the spaces betweenthe first and second spacers SP1 and SP2.

In an exemplary embodiment, the capping patterns CP may be selectivelygrown from the barrier pattern 134 exposed from the second spacer SP2and the residual pattern 137. In this case, the capping patterns CP mayinclude the same material as the barrier pattern 134. For example, thecapping patterns CP may include TiN. The selective growth of the cappingpatterns CP from the barrier patterns 134 may be achieved by repeatingseveral times a cycle that includes the followings: supplying a firstsource gas (e.g., NH₃) adsorbed on the barrier pattern 134, but not onthe metal pattern 136, the first and second spacers SP1 and SP2, and theinsulation pattern 120; purging the first source gas not adsorbed on thebarrier pattern 134; supplying a precursor (e.g., TiCl₄) including adepositing target material and chemically combining the precursor andthe first source gas to form a mono-atomic metal nitride layer on thebarrier pattern 134; and purging the precursor not reacted with thefirst source gas. The present inventive concept is not limited thereto.For example, the supply order of the first source gas and the precursormay be reversed. The present inventive concept is not limited thereto.For example, the first source gas and the precursor may be supplied atsubstantially the same time. For example, the TiN may be supplied by amix of processes including a chemical vapor deposition (CVD) process, aPVD process, or metal-organic chemical vapor deposition (MOCVD) processusing metal-organic precursors such as Tetrakis(dimethylamino)titanium(TDMAT).

In an exemplary embodiment, as shown in FIG. 11C, the capping patternsCP may be selectively grown from the metal pattern 136 of each of thelanding patterns LP exposed from the second spacer SP2 and the residualpattern 137. The capping patterns CP may include the same material asthe metal pattern 136. For example, the capping patterns CP may includetungsten (W). The selective growth of the capping pattern CP from themetal pattern 136 may be achieved by repeating several times a chemicalvapor deposition (CVD) cycle that includes the followings: supplying afirst source gas (e.g., hydrogen (H₂), monosilane (SiH₄), or diborane(B₂H₆)) adsorbed on the metal pattern 136 but not on the barrier pattern134, the first and second spacers SP1 and SP2, and the insulationpattern 120; purging the first source gas not adsorbed on the metalpattern 136; supplying a precursor (e.g., tungsten halide such astungsten hexafluoride (WF₆) and tungsten hexachloride (WCl₆), or ametal-organic gas including tungsten element) including a depositingtarget material and chemically combining the precursor and the firstsource gas to form a mono-atomic metal layer on the metal pattern 136;and purging the precursor not reacted with the first source gas. Thepresent inventive concept is not limited thereto. For example, thesupply order of the first source gas and the precursor may be reversed.For example, the first source gas and the precursor may be supplied atsubstantially the same time.

During the formation of the capping patterns CP, upper metal patterns MPmay be selectively grown from top surfaces of the metal patterns 136exposed from the residual patterns 137. The upper metal pattern MP mayinclude, for example, tungsten (W).

A first gap-fill layer 138 a and a second gap-fill layer 138 b may besequentially formed in the internal space O. The first gap-fill layer138 a may conformally cover an inner surface of the inner spacer O. Forexample, the first gap-fill layer 138 a may cover or enclose upperportions of the air spacers ASP incompletely covered with the cappingpatterns CP. The second gap-fill layer 138 b may completely fill theinner space O. The first and second gap-fill layers 138 a and 138 b mayinclude, for example, silicon nitride.

According to an exemplary embodiment of the present inventive concept,in the inner space O between the landing pads LP, the capping patternsCP each may be selectively grown from the barrier pattern 134, or themetal pattern 136, or both, each of which portions constitutes a portionof the sidewall of each of the landing pads LP exposed through thesecond spacer SP2, and may partially or completely cover the upperportion of the space between the first and second spacers SP1 and SP2,thereby defining the air spacer ASP between the first and second spacersSP1 and SP2. Therefore, in a process for forming the first gap-filllayer 138 a in the inner space O, the capping patterns CP each mayprevent the first gap-fill layer 138 a from flowing into the spacebetween the first and second spacers SP1 and SP2. In addition, the airspacer ASP may be prevented from reduction of its area. As a result, itmay be possible to prevent or suppress increase of parasitic capacitancebetween the bit lines BL and the storage node contacts BC.

Referring back to FIGS. 1 and 2, data storage members DSM may be formedon the landing pads LP. The data storage members DSM may be, forexample, a capacitor. The formation of the data storage members DSM mayinclude forming on the landing pads LP bottom electrodes BE, adielectric layer DL, and a top electrode TE.

While the present inventive concept has been shown and described withreference to exemplary embodiments thereof, it will be apparent to thoseof ordinary skill in the art that various changes in form and detail maybe made therein without departing from the spirit and scope of theinventive concept as defined by the following claims.

What is claimed is:
 1. A semiconductor memory device comprising: asubstrate; a device isolation layer disposed in the substrate definingan active region extending in a first direction; first conductive linesdisposed in the active region and extending in a second directioncrossing the first direction; a second conductive line disposed on theactive region between the first conductive lines and extending in athird direction crossing the first direction and the second direction; abit line node contact disposed between the active region and the secondconductive line; a landing pad disposed on an edge portion of the activeregion; a storage node contact between the landing pad and the edgeportion of the active region; a buried pattern disposed between the bitline node contact and the storage node contact; a first spacer disposedbetween a sidewall of the second conductive line and the landing pad; anair spacer disposed between the first spacer and the landing pad; and acapping pattern protruding from a sidewall of the landing and disposedon the air spacer, wherein the capping pattern is spaced apart from thefirst spacer.
 2. The semiconductor memory device of claim 1, wherein thecapping pattern partially covers an upper portion of the air spacer. 3.The semiconductor memory device of claim 1, wherein the capping patterncomprises a barrier pattern and a metal pattern stacked on the edgeportion of the active region, wherein the capping pattern includes thesame material as the barrier pattern, wherein the capping patternincludes a different material with a material of the metal pattern. 4.The semiconductor memory device of claim 1, wherein the capping patterncomprises a barrier pattern and a metal pattern stacked disposed on theactive region, wherein the capping pattern includes a different materialwith a material of the barrier pattern, wherein the capping patternincludes the same material as the metal pattern.
 5. The semiconductormemory device of claim 1, further comprising a second spacer disposedbetween the landing pad and the air spacer below the capping pattern,wherein the capping pattern is in contact with the second spacer.
 6. Thesemiconductor memory device of claim 1, further comprising a secondspacer disposed between the landing pad and the air spacer below thecapping pattern, wherein the capping pattern is spaced apart from thesecond spacer.
 7. The semiconductor memory device of claim 1, furthercomprising a second spacer disposed between the landing pad and the airspacer below the capping pattern, wherein the second spacer is covered aportion of the sidewall of the landing pad.
 8. The semiconductor memorydevice of claim 1, further comprising a gap fill layer disposed on thecapping pattern, wherein the gap fill layer covers a portion of thesidewall of the landing pad above the capping pattern and a top surfaceof the capping pattern.
 9. The semiconductor memory device of claim 1,further comprising a gap fill layer disposed on the capping pattern,wherein the gap fill layer covers a top surface of the capping pattern,wherein the gap fill layer completely covers an upper portion of the airspacer exposed by the capping pattern.
 10. The semiconductor memorydevice of claim 9, wherein the gap fill layer is in contact with thefirst spacer.
 11. The semiconductor memory device of claim 9, whereinthe gap fill layer is spaced apart from the first spacer.
 12. Thesemiconductor memory device of claim 1, further comprising a gap filllayer disposed on the capping pattern, wherein the gap fill layer coversa top surface of the capping pattern, wherein a level of a lowermostupper surface of the gap fill layer from an upper surface of thesubstrate is lower than a level of top surface of the capping patternfrom the upper surface of the substrate.
 13. The semiconductor memorydevice of claim 1, further comprising a gap fill layer disposed on thecapping pattern, wherein the gap fill layer covers a top surface of thecapping pattern, wherein a level of a lowermost upper surface of the gapfill layer from an upper surface of the substrate is higher than a levelof top surface of the capping pattern from the upper surface of thesubstrate.
 14. The semiconductor memory device of claim 1, furthercomprising a data storage member disposed on the landing pad.
 15. Asemiconductor memory device comprising: a substrate; a device isolationlayer disposed in the substrate defining an active region extending in afirst direction; first conductive lines disposed in the active regionand extending in a second direction crossing the first direction; asecond conductive line disposed on the active region between the firstconductive lines and extending in a third direction crossing the firstdirection and the second direction; a bit line node contact disposedbetween the active region and the second conductive line; a landing paddisposed on an edge portion of the active region; a storage node contactbetween the landing pad and the edge portion of the active region; aburied pattern disposed between the bit line node contact and thestorage node contact an air spacer disposed between a sidewall of thesecond conductive line and the landing pad; and a capping patternprotruding from a sidewall of the landing pad, wherein the cappingpattern partially covers an upper portion of the air spacer.
 16. Thesemiconductor memory device of claim 15, further comprising a gap filllayer on the capping pattern, wherein the gap fill layer completelycovers the upper portion of the air spacer exposed by the cappingpattern.
 17. The semiconductor memory device of claim 15, wherein thecapping pattern comprises a barrier pattern and a metal pattern stackedon the edge portion of the active region, wherein the capping patternincludes the same material as the barrier pattern, wherein the cappingpattern includes a different material with a material of the metalpattern.
 18. The semiconductor memory device of claim 15, wherein thecapping pattern comprises a barrier pattern and a metal pattern stackedon the edge portion of the active region, wherein the capping patternincludes a different material with a material of the barrier pattern,wherein the capping pattern includes the same material as the metalpattern.
 19. A semiconductor memory device comprising: a substrate; adevice isolation layer disposed in the substrate defining an activeregion extending in a first direction; first conductive lines disposedin the active region and extending in a second direction crossing thefirst direction; a second conductive line disposed on the active regionbetween the first conductive lines and extending in a third directioncrossing the first direction and the second direction; a bit line nodecontact disposed between the active region and the second conductiveline; a landing pad disposed on an edge portion of the active region; astorage node contact between the landing pad and the edge portion of theactive region; a buried pattern disposed between the bit line nodecontact and the storage node contact; an air spacer disposed between asidewall of the second conductive line and the landing pad; a cappingpattern protruding from a sidewall of the landing pad; and a gap filllayer on the capping pattern; wherein the capping pattern covers a firstupper portion of the air spacer, wherein the gap fill layer covers asecond upper portion the air spacer.
 20. The semiconductor memory deviceof claim 19, wherein the capping pattern includes the same material asthe material of the landing pad, wherein the gap fill layer includes aninsulating material.